1、Extract feature list for block IP verification plan with fully understanding of design spec;
2、Responsible for block IP & SoC level UVM verification environment generation, development, maintenance and improvement;
3、Random sequences & test cases creation with CRV flow;
4、Strong debug skills for tracing waves in Verdi and UVM dynamic environment;
5、Work closely with RTL designers and architects to develop SV reference model in UVM predictor;
6、Know HVP or CDV flow, writing covergroups / coverpoints / bins to collect functional coverage
7、Solid experiences with C, Shell, Makefile, Python and so on;
8、Good knowledge of Ethernet protocol and IEEE 802.3 are highly preferred;
9、Participate in gate-level simulation;
10、Proficient in writing SVA is a big plus;
11、Cutting-edge verification technology such as vc formal or JasperGold is preferred;
12、Close collaboration with architect, design, SW/FW, FPGA teams to close all chip issues & bugs;
13、Assist FPGA & emulation teams to perform FPGA prototyping simulation;
14、Complex SoC verification experiences are highly preferred;
15、Familiar with Linux environment and SVN;
16、Excellent communication skills and fluent English with counterparts in Shanghai, Suzhou and Singapore.
Job requirements:
1、Bachelor degree of Computer Science, EE or equivalent (fresh year is also acceptable);
2、Familiar with Linux basic commands, Perl(or Python) scripting language;
3、Master Verilog,System Verilog, master C/C ++ is better;
4、Proficient in using VCS,NC-Verilog,modelSim and other mainstream EDA simulation tools;
5、Proficient in chip verification process and UVM verification methodology, able to use UVM to build chip modules and system-level verification platform;